View CY7C1061DV33-10BVJXI_6666885.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c1061dv33 16-mbit (1 m x 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05476 rev. *g revised january 18, 2011 features high speed ? t aa = 10 ns low active power ? i cc = 175 ma at 10 ns low cmos standby power ? i sb2 = 25 ma operating voltages of 3.3 0.3v 2.0v data retention automatic power down when deselected ttl compatible inputs and outputs easy memory expansion with ce 1 and ce 2 features available in pb-free 54-pin tsop ii and 48-ball vfbga packages offered in single ce and dual ce options functional description the cy7c1061dv33 is a high performance cmos static ram organized as 1,048,576 words by 16 bits. to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). to read from the device, take chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specif ied by the address pins appears on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 12 for a complete description of read and write modes. the input or output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when the device is deselected (ce 1 high/ce 2 low), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce 1 low, ce 2 high, and we low). the cy7c1061dv33 is available in a 54-pin tsop ii package with center power and ground (rev olutionary) pinout, and 48-ball vfbga packages. selection guide description ? 10 unit maximum access time 10 ns maximum operating current 175 ma maximum cmos standby current 25 ma 15 16 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 1m x 16 array a 0 a 12 a 14 a 13 a a a 17 a 18 a 10 a 11 i/o 0 ? i/o 7 oe i/o 8 ? i/o 15 ce 1 we ble bhe a 9 a 19 ce 2 logic block diagram [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 2 of 17 contents pin configuration ............................................................. 3 maximum ratings ............................................................. 6 operating range ............................................................... 6 dc electrical characteristics .......................................... 6 thermal resistance .......................................................... 7 capacitance ...................................................................... 7 ac switching characteristics ......................................... 8 data retention characteristics ....................................... 9 over the operating range ............................................... 9 switching waveforms ...................................................... 9 truth table ...................................................................... 12 ordering information ...................................................... 13 ordering code definitions ..... .................................... 13 package diagrams .......................................................... 14 acronyms ........................................................................ 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17 [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 3 of 17 pin configuration notes 1. nc pins are not connected on the die. 2. in bvxi package, ball h6 is msb address a19 and ball g2 is nc; in bvjxi package, ball h6 is nc and ball g2 is msb address a19 . we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc a 18 a 19 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss figure 1. 48-ball vfbga dual chip enable(-bvxi) (top view) [1, 2] we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss figure 2. 48-ball vfbga dual chip enable(-bvjxi) (top view) [1, 2] [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 4 of 17 note 3. nc pins are not connected on the die. 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 i/o 11 18 17 20 19 23 28 25 24 22 21 27 26 v ss i/o 10 i/o 12 v cc i/o 13 i/o 14 v ss a 16 a 17 a 11 a 12 a 13 a 14 i/o 0 a 15 i/o 7 i/o 9 v cc i/o 8 i/o 15 a 19 a 4 a 3 a 2 a 1 ce 1 v cc we ce 2 ble nc v ss oe a 8 a 7 a 6 a 5 a 0 nc a 9 bhe a 10 10 a 18 46 45 47 50 49 48 51 54 53 52 i/o 2 i/o 1 i/o 3 v ss v cc v ss i/o 6 i/o 5 v cc i/o 4 figure 3. 54-pin tsop ii (top view) [3] [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 5 of 17 notes 4. nc pins are not connected on the die. 5. in bv1xi package, ball a6 is nc, ball h6 is nc and ball g2 is msb address a19. bv1xi package has only single chip enable (ce ). we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe nc a 17 a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss figure 4. 48-ball vfbga single chip enable (-bv1xi) (top view) [4, 5] [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 6 of 17 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [6] ...?0.5 v to +4.6 v dc voltage applied to outputs in high z state [6] .................................. ?0.5 v to v cc + 0.5 v dc input voltage [6] .............................. ?0.5 v to v cc + 0.5 v current into outputs (low)....... .................................. 20 ma static discharge voltage............ ...............................>2001 v (mil-std-883, method 3015) latch up current ..................................................... >200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ? c 3.3 v ? 0.3 v dc electrical characteristics over the operating range parameter description test conditions ? 10 unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih input high voltage ? 2.0 v cc + 0.3 v v il input low voltage [6] ? ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, f = f max = 1/t rc, i out = 0 ma cmos levels 175 ma i sb1 automatic ce power down current ? ttl inputs max v cc , ce 1 > v ih , ce 2 < v il, v in > v ih or v in < v il , f = f max ?30ma i sb2 automatic ce power down current ?cmos inputs max v cc , ce 1 > v cc ? 0.3v, ce 2 < 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 ?25ma note 6. v il (min) = ?2.0 v and v ih (max) = v cc + 2 v for pulse durations of less than 20 ns. [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 7 of 17 capacitance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions tsop ii vfbga unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 6 8 pf c out i/o capacitance 8 10 pf thermal resistance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions tsop ii vfbga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four layer printed circuit board 24.18 28.37 ? c/w ? jc thermal resistance (junction to case) 5.40 5.79 ? c/w figure 5. ac test loads and waveforms [7] 90% 10% 3.0 v gnd 90% 10% all input pulses 3.3 v output 5 pf* including jig and scope (b) r1 317 ? r2 351 ? rise time: fall time: > 1 v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5 v 30 pf* * capacitive load consists of all components of the test environment high-z characteristics: (a) > 1 v/ns note 7. valid sram operation does not occur until the pow er supplies have reached the minimum operating v dd (3.0 v). 100 ? s (t power ) after reaching the minimum operating v dd , normal sram operation begins including reduction in v dd to the data retention (v ccdr , 2.0 v) voltage. [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 8 of 17 ac switching characteristics over the operating range [8] parameter description ? 10 unit min max read cycle t power v cc (typical) to the first access [9] 100 ? ? s t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce 1 low/ce 2 high to data valid ? 10 ns t doe oe low to data valid ? 5 ns t lzoe oe low to low z 1 ? ns t hzoe oe high to high z [10] ?5 ns t lzce ce 1 low/ce 2 high to low z [10] 3? ns t hzce ce 1 high/ce 2 low to high z [10] ?5 ns t pu ce 1 low/ce 2 high to power up [11] 0? ns t pd ce 1 high/ce 2 low to power down [11] ?10 ns t dbe byte enable to data valid ? 5 ns t lzbe byte enable to low z 1 ? ns t hzbe byte disable to high z ? 5 ns write cycle [12, 13] t wc write cycle time 10 ? ns t sce ce 1 low/ce 2 high to write end 7 ? ns t aw address setup to write end 7 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 7 ? ns t sd data setup to write end 5.5 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [10] 3? ns t hzwe we low to high z [10] ?5 ns t bw byte enable to end of write 7 ? ns notes 8. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, and input pulse levels of 0 to 3.0 v. test conditions for the read cycle use output loading shown in part a) of ac test loads and waveforms[7] , unless specified otherwise. 9. t power gives the minimum amount of time that the power supply is at typical v cc values until the first memory access is performed. 10. t hzoe , t hzce , t hzwe , t hzbe , t lzoe , t lzce , t lzwe , and t lzbe are specified with a load capacitance of 5 pf as in (b) of ac test loads and waveforms[7] . transition is measured ? 200 mv from steady state voltage. 11. these parameters are guaranteed by design and are not tested. 12. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . chip enables must be active and we and byte enables must be low to initiate a write, and the transition of any of these signal s can terminate. the input data setup and hold timing should be r eferenced to the edge of the signal that terminates the write. 13. the minimum write cycle time for write cycle no. 2 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 9 of 17 data retention characteristics over the operating range parameter description conditions min max unit v dr v cc for data retention ? 2 ? v i ccdr data retention current v cc = 2 v, ce 1 > v cc ? 0.2 v, ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ?25ma t cdr [14] chip deselect to data retention time ? 0 ? ns t r [15] operation recovery time ? t rc ?ns figure 6. data retention waveform [16] switching waveforms figure 7. read cycle no. 1 [17, 18] 3.0 v 3.0 v t cdr v dr > 2 v data retention mode t r ce v cc previous data valid data valid rc t aa t oha t rc address data out notes 14. tested initially and after any design or proce ss changes that may affect these parameters. 15. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 ? s or stable at v cc(min.) > 50 ? s. 16. for all packages except -bv1xi, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. for -bv1xi package, ce refers to ce . 17. the device is continuously selected. oe , ce = v il , bhe , ble or both = v il . 18. we is high for read cycle. [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 10 of 17 figure 8. read cycle no. 2 (oe controlled) [19, 20, 21] figure 9. write cycle no. 1 (ce controlled) [19, 22, 23] switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb t hd t sd t sce t sa t ha t aw t pwe t wc bw t data i/o address ce we bhe , ble notes 19. for all packages except -bv1xi, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. for -bv1xi package, ce refers to ce . 20. we is high for read cycle. 21. address valid before or similar to ce transition low. 22. data i/o is high impedance if oe , bhe , and/or ble = v ih . 23. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 11 of 17 figure 10. write cycle no. 2 (we controlled, oe low) [24, 25, 26] figure 11. write cycle no. 3 (ble or bhe controlled) [24] switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw t sa t lzwe t hzwe data i/o address ce we bhe ,ble t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble ce we notes 24. for all packages except -bv1xi, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. for -bv1xi package, ce refers to ce . 25. data i/o is high impedance if oe , bhe , and/or ble = v ih . 26. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 12 of 17 truth table for all packages except -bv1xi ce 1 ce 2 oe we ble bhe i/o 0 ? io 7 i/o 8 ? i/o 15 mode power hxxxxxhigh z high z power down standby (i sb ) xlxxxxhigh z high z power down standby (i sb ) l h l h l l data out data out read all bits active (i cc ) l h l h l h data out high z read lower bits only active (i cc ) l h l h h l high z data out read upper bits only active (i cc ) l h x l l l data in data in write all bits active (i cc ) l h x l l h data in high z write lower bits only active (i cc ) l h x l h l high z data in write upper bits only active (i cc ) l h h h x x high z high z selected, outputs disabled active (i cc ) truth table for -bv1xi package only ce oe we ble bhe i/o 0 ? i/o 7 i/o 8 ? i/o 15 mode power h xxxxhigh z high z power down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high z read lower bits only active (i cc ) l l h h l high z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high z write lower bits only active (i cc ) l x l h l high z data in write upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 13 of 17 ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c1061dv33-10zsxi 51-85160 54-pin tsop ii (pb-free) industrial cy7c1061dv33-10bvxi 51-85178 48-ball vfbga (8 9.5 1 mm) (pb-free) (dual chip enable) CY7C1061DV33-10BVJXI 48-ball vfbga (8 9.5 1 mm) (pb-free) (dual chip enable - jedec compatible) cy7c1061dv33-10bv1xi 48-ball vfbga (8 9.5 1 mm) (pb-free) (single chip enable) ordering code definitions temperature range: i = industrial package type: xxx = zsx or bvx or bvjx zsx = 54-pin tsop ii (pb-free) bvx = 48-ball vfbga (pb-free) bvjx = 48-ball vfbga (pb-free) speed: 10 ns v33 = voltage range (3 v to 3.6 v) d = c9, 90 nm technology 1 = data width 16-bits 06 = 16-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - 10 xxx 7 06 d i v33 1 [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 14 of 17 package diagrams figure 12. 54-pin tsop type ii 51-85160 *a [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 15 of 17 figure 13. 48-ball vfbga (8 x 9.5 x 1 mm) package diagrams (continued) 51-85178 *a acronyms acronym description bhe byte high enable ble byte low enable cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory tsop thin small outline package vfbga very fine ball gird array we write enable [+] feedback
cy7c1061dv33 document number: 38-05476 rev. *g page 16 of 17 document history page document title: cy7c1061dv33 16 -mbit (1 m x 16) static ram document number: 38-05476 rev. ecn no. orig. of change submission date description of change ** 201560 swi see ecn advance data sheet for c9 ipp *a 233748 rkf see ecn ac, dc parameters are modified as per eros (specification number 01-2165) added pb-free devices in the ordering information *b 469420 nxr see ecn converted from advance information to preliminary corrected typo in the document title removed ?8 and ?12 speed bins from product offering removed commercial operating range changed 2g-ball of fbga and pin 40 of tsopii from dnu to nc included the maximum ratings for static discharge voltage and latch up current on page 3 changed i cc(max) from 220 ma to 125 ma changed i sb1(max) from 70 ma to 30 ma changed i sb2(max) from 40 ma to 25 ma specified the overshoot specification in footnote 1. updated the ordering information table *c 499604 nxr see ecn added note 1 for nc pins updated test condition for i cc in dc electrical characteristics table updated the 48-ball fbga package *d 1462583 vkn/aesa see ecn converted from preliminary to final changed i cc specification from 125 ma to 175 ma updated thermal specs *e 2704415 vkn/pyrs 05/11/09 included 48 fbga -bvjxi package added footnote #2 *f 3109102 aju 12/13/2010 added ordering code definitions . updated package diagrams . *g 3126531 pras 01/03/2011 added 48-ball vfbga single chip enable package. updated ordering information. added acronyms. [+] feedback
document number: 38-05476 rev. *g revised january 18, 2011 page 17 of 17 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1061dv33 ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

▲Up To Search▲

Price & Availability of CY7C1061DV33-10BVJXI

	To Download CY7C1061DV33-10BVJXI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .